Structure of Instructions in CPU Questions with Solutions
This topic covers how a CPU actually executes a program. Every instruction passes through the instruction cycle: fetch the instruction from memory, decode it, execute it, and store the result. An instruction is made up of an operation code (opcode), which says what to do, and operands, which say what data to use. The topic also covers instruction formats (zero-, one-, two- and three-address instructions), addressing modes (immediate, direct, indirect, register, indexed and relative addressing), and important registers such as the program counter (PC), instruction register (IR), memory address register (MAR) and memory data register (MDR). Exam questions test which register holds the address of the next instruction (the program counter), the stages of the instruction cycle, and identifying the addressing mode used in an example instruction. Basic ideas of RISC and CISC architectures are also asked. Practise the instruction structure questions below. Each answer includes an explanation.
- Q1.
Which of the following statements about the fetch–decode–execute cycle in a CPU are correct?
A. II and III onlyB. I and II onlyC. I, II and III onlyD. III and IV onlymediumAsked in NIMCET 2026View solution › - Q2.
In computer science, data hazard occurs when
A. pipeline changes the order of read/write access to operandsB. performance lossC. machine size is limitedD. some functional unit is not fully pipelinedmediumAsked in TCS ExamView solution › - Q3.
Which of the following is the elementary operation executed on data stored in registers?
A. BitoperationB. MacrooperationC. MicrooperationD. ByteoperationmediumAsked in TCS ExamView solution › - Q4.
_______ is the number of bits in the internal data bus of a processor. It is also the number of bits a processor can process at a time.
A. Control UnitB. Data LengthC. Word LengthD. bytemediumAsked in TCS ExamView solution › - Q5.
An index register in a digital computer is used for:
A. pointing to the stack address.B. indirect addressing.C. keeping track of the number of times a loop is executed.D. address modification.mediumAsked in NIMCET 2009View solution › - Q6.
A microprogrammed control unit is:
A. faster than a hardwired unit.B. slower than a hardwired unit.C. used to make it easy to implement new instructions.D. Both (B) and (C).mediumAsked in NIMCET 2009View solution › - Q7.
To fetch data from secondary memory, which one of the following registers is used?
A. MARB. PCC. IRD. MBRmediumAsked in NIMCET 2021View solution › - Q8.
Which of the following components is not a part of an instruction format in CPU processing?
A. OpcodeB. Register fileC. Source operandD. Destination operandmediumAsked in NIMCET 2024View solution › - Q9.
Which of the following components is used to establish a communication link between the CPU and the peripheral devices to transfer data?
A. Index registerB. Memory address registerC. Memory data registerD. Instruction registermediumAsked in NIMCET 2024View solution › - Q10.
Which of the statements given above are correct?
A. 2, 3 and 4 onlyB. 1, 3 and 4 onlyC. 1, 2, 3 and 4D. 1, 2 and 4 onlymediumAsked in NIMCET 2025View solution › - Q11.
Consider a system with a CPU having 6 registers and 32-bit instructions. The maximum possible size of the main memory is 512 KB ( ). Each instruction takes two registers and one memory address as operands. Which one of the following correctly gives the maximum possible number of distinct instructions in the instruction set of the CPU?
A. 1024B. 256C. 128D. 64mediumAsked in NIMCET 2025View solution › - Q12.
In an instruction execution pipeline, the earliest that the instruction TLB and data TLB can be accessed are
A. Fetch stage and memory stage respectivelyB. Memory stage and memory stage respectivelyC. Memory stage and execute stage respectivelyD. Fetch stage and fetch stage respectivelymediumAsked in NIMCET 2025View solution ›