Structure of Instructions in CPU Questions with Solutions
This topic covers how a CPU actually executes a program. Every instruction passes through the instruction cycle: fetch the instruction from memory, decode it, execute it, and store the result. An instruction is made up of an operation code (opcode), which says what to do, and operands, which say what data to use. The topic also covers instruction formats (zero-, one-, two- and three-address instructions), addressing modes (immediate, direct, indirect, register, indexed and relative addressing), and important registers such as the program counter (PC), instruction register (IR), memory address register (MAR) and memory data register (MDR). Exam questions test which register holds the address of the next instruction (the program counter), the stages of the instruction cycle, and identifying the addressing mode used in an example instruction. Basic ideas of RISC and CISC architectures are also asked. Practise the instruction structure questions below. Each answer includes an explanation.
- Q21.
Consider a system with a CPU having 6 registers and 32-bit instructions. The maximum possible size of the main memory is 512 KB ( ). Each instruction takes two registers and one memory address as operands. Which one of the following correctly gives the maximum possible number of distinct instructions in the instruction set of the CPU?
A. 1024B. 256C. 128D. 64mediumAsked in NIMCET 2025View solution › - Q22.
In an instruction execution pipeline, the earliest that the instruction TLB and data TLB can be accessed are
A. Fetch stage and memory stage respectivelyB. Memory stage and memory stage respectivelyC. Memory stage and execute stage respectivelyD. Fetch stage and fetch stage respectivelymediumAsked in NIMCET 2025View solution ›